Why 2-port PDN Impedance Measurement of a Power Supply is Important - An example with the TI TPSM8D6C24

Jan 235 min read

It is an exciting time to be a hardware, package, and PCB designer supporting power integrity applications. The latest power supplies and Voltage Regulator Modules (VRM) available on the market are continuing to increase in current capacity to support next-generation semiconductors likes FPGAs, ASICs, and GPUs used for AI/ML applications in data centers, as well as for RF, radar, and airborne applications in the aerospace and defense industry. There are VRMs available today with 100A (continuous) per square centimeter current density.

That being said, if you're looking to select a power supply to use in your design, what are some considerations or steps to take before dropping the power supply or VRM into your schematic?

What is the Value of Impedance Measurements?

As a starting point, we recommend always measuring the power supply or VRM on a vendor evaluation board (EVM) or building your own EVM if a vendor version is not available. The impedance measurement, which is measured in ohms, can tell us a lot of information about the power supply's control loop, including stability. Further, we can more easily assess if the current PDN design with the power supply has sufficient capacitance for our desired application. The simple takeaway here is that noise follows impedance, so any high-Q impedance peaks in the PDN will almost always correspond to noise seen in the voltage ripple, transient response, and EMC/EMI measurements.

Let's look at an example that will use the TPSM8D6C24 from Texas Instruments. The TPSM8D6C24 is a highly integrated, easy-to-use, non-isolated DC/DC buck power module with PMBus. It provides two 35-A independent outputs or a single stacked 2-phase 70-A output. Two modules can be stacked for a 4-phase 140-A output.

Figure 1 shows the impedance measurement setup with the TPSM8D6C24EVM-2PH using the Bode 100 Vector Network Analyzer, J2113A Differential Amplifier, P2102A 2-Port Probe, and P9610A Mixed Mode Power Supply. The Bode 500 VNA could also be used to do this measurement instead of the Bode 100 if desired. The EVM is provided 12,V and the output is set to 1V.

If you want to learn more about why using the P2102A 2-port probe is important for PDN impedance measurements, then check out this blog.

**Figure 1 -** **TPSM8D6C24EVM-2PH Impedance Measurement Setup**

The impedance measurement result is shown in Figure 2. The high-Q seen at 81 kHz is a strong indicator that this VRM's control loop is unstable.

Using the Non-Invasive Stability Measurement (NISM) invented by Steve Sandler of Picotest, we see a stability margin of 18.7 degrees, as shown in Figure 3, which aligns with our initial observation.

**Figure 2 -** **TPSM8D6C24EVM-2PH Impedance Measurement Results**

**Figure 3 -** **TPSM8D6C24EVM-2PH Impedance Measurement Stability Analysis using NISM**

How to Fix the VRM Instability

So, what would it take to fix this instability in this design?

As shown in Figure 4, the peak inductance at 81 kHz is 12.2 nF, calculated by solving EQ(1) for Lpeak.

Where XL is the impedance peak 81 kHz.

Solving for Lpeak yields EQ(2)

To determine the minimum amount of capacitance needed to flatten the 12.2 nH impedance peak at 81 kHz, we will solve EQ(3) for C. We will then arbitrarily set Zo equal to our desired target impedance, which is 1.5 mOhm, as reflected in Figure 4.

By EQ(4), this yields an answer of 5.4 mF of additional capacitance required to fix this control loop instability on the VRM. This is very significant, and it increases the total footprint (to add more caps) for this VRM design. This VRM architecture is not useful (or practical) for space-constrained Aerospace and Defense applications.

As shown by Figure 5 from the VRM datasheet, this PMBus-controlled VRM has multiple internal registers that can be adjusted to change the control loop settings, such as the gain selection of the current loop, which sets slope compensation and compensation values. All of these will directly impact the VRM's performance and stability. Working with Texas Instruments, we received an updated register configuration, which we loaded on the VRM.

TPSM8D6C24 Average Current Mode Control Block Diagram — **Figure 5 -** **TPSM8D6C24** **Average Current Mode Control Block Diagram**

Figure 6 depicts the updated impedance result after TI provided updated register settings for the VRM that they optimized. As we can see by using NISM, this design is just barely greater than 30 degrees of stability margin. This is not what I would call as stable.

**Figure 6 -** **TPSM8D6C24EVM-2PH Impedance Measurement with Updated Register Settings - Stability Analysis using NISM**

If we want to increase our stability, we will again need to add more capacitance. By again using EQ(5), we calculated that an additional 2.1 mF of capacitance is required to fix this control loop instability on the VRM. This is still very significant, and it still increases the total footprint (to add more caps) around this VRM design. This VRM architecture is not useful (or practical) for space-constrained Aerospace and Defense applications or even data center applications.

Again, this shows why you can never trust a vendor reference design. If you do not have a good model, this could have been caught by acquiring an evaluation board from the vendor or building your own. At Signal Edge Solutions, this is why we make models and support these measurements. If you don’t have a model, then this shows why it is essential to measure a design from a vendor before you copy this design into your design.

Wrapping Up:

For a 70 Amp EVM design with currently QTYx4 470uF tantalum caps, that is not even close to enough capacitance to have a stable design. Let's consider this from another perspective: at 30kHz, your impedance (from the VRM control loop) is 1.3 mOhm. So, if you have a 60A load on this PDN, your DC drop is already 78mV on a 0.8V supply. That is quite high and usually not acceptable as a DC drop for any design. This impedance must be lower for this current capacity. If you want to use this VRM to help make the load look sexy, the EVM PDN design must be improved, and the VRM control settings could be improved further.

Was any power integrity analysis done on this VRM design before the EVM design was released? The point is that all of this could have been caught easily.

Some quick measurements and math show that we still need to add 2.1 mF of additional capacitance to the board to fix this stability issue. Although that is better than the 5.4 mF we showed initially, 2.1 mF is not insignificant.

Why 2-port PDN Impedance Measurement of a Power Supply is Important - An example with the TI TPSM8D6C24

What is the Value of Impedance Measurements?

How to Fix the VRM Instability

Wrapping Up:

References:

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