In today’s world of high-power, high-current designs, especially in AI and data center ASICs, Power Integrity (PI) challenges are becoming increasingly complex. One of the most critical aspects of ensuring successful power delivery is managing the core voltage, particularly when dealing with multi-chip designs that feature multiple core voltages within a single package.
Our PCBs need to be able to handle high-power levels while maintaining reliable performance. The materials we use may not drastically change, but their ability to withstand such power demands requires careful consideration. Understanding the power requirements of our rails is essential for overcoming these challenges.
Designing the Stack-Up for Power Integrity
Selecting the right PCB stack-up to accommodate high-power rails is a key aspect of ensuring PI. While the VRM (Voltage Regulator Module) plays a role in power distribution, the design of the stack-up especially the selection of copper thickness - Is something that can and should be addressed early in the design phase. By doing so, we can make informed decisions about the material specifications before jumping into detailed simulations.
The Role of Predictive Calculators in IR Drop
This blog introduces a new calculator designed to predict the IR drop in a PCB without needing to run full simulations at the initial design stage. By providing rough estimates of the IR drop, this tool enables engineers to make informed decisions about copper thickness early on in the process.
Key Factors for High-Power PCB Design:
Stack-Up Selection: An effective stack-up design should balance the separation of power and signal layers while minimizing via inductance.
Thermal Management: Managing high current traces requires careful consideration of thermal properties to minimize power loss.
Loss Estimation: Estimating power loss early in the design process helps guide crucial design decisions.
Simulation Tools: Accurate predictive tools help address design challenges with greater precision, offering a clearer path forward.
While there are many IR drop calculators available online, most rely on basic parameters like area and temperature rise. While these provide a good first approximation, they don’t accurately capture the complexities of high-power designs with multiple power rails. As a result, engineers may end up with unrealistic trace width estimates, which can lead to misunderstandings about the actual copper thickness required for the design.
Example: IR Drop Calculation Using IPC-2221
Let’s walk through an example based on typical parameters for a high-power design:
Current: 2,000A
Thickness: 14 mils
Temperature Rise: 10°C
Ambient Temperature: 55°C
Trace Length: 4000 mils
According to IPC-2221, we can estimate the area and width using the following formulas:
From IPC-2221 internal layers: k = 0.024,b = 0.44,c = 0.725
From IPC-2221 external layers: k = 0.048,b = 0.44,c = 0.725
After calculating the area and trace width, we can compute the resistance:
Using the above parameters, we would get the following results:
Area = 1515094.3 mils^2
Required Trace Width = 109.94 Inch
Resistance = 5 uΩ
Voltage Drop = 1 mV
Power Loss = 2 W
At first glance, a trace width of 109 inches may seem acceptable. However, this is a physically unrealistic number. The calculated PCB resistance of 5μΩ with only 2W of power loss is far from what we would expect in a real-world scenario, especially when considering high-power designs. The true trace width will likely be much smaller, and the resulting IR drop will be far higher than the calculated values.
The Importance of Realistic Trace Width Predictions
The initial calculation provides an unrealistic view of our design. The actual trace width will not meet the 109 inches required by these calculations, and this discrepancy highlights the importance of understanding copper thickness requirements early on.
Before diving into complex simulations, we need to predict the real trace width that will meet the power requirements and ensure our design can handle the IR drop effectively. This first step is critical in minimizing power loss and preventing VRM compensation from becoming an afterthought.
Essential Considerations for High-Power Stack-Up Design:
Width: An accurate initial input to estimate the trace dimensions.
Number of Vias: Impacts current distribution and resistance.
Drill Diameter: Affects via impedance and overall design performance.
Package Pitch: Influences the constraints on trace width and spacing.
By using these inputs, a predictive calculator can give us a more realistic estimate of the required trace width, which will ultimately help in predicting the IR drop before performing post-layout EM simulations.
Below is a real example based on the Picotest 2KAmp design which was presented at DesignCon 2025:
Example: IR Drop Calculation Using my calculator
Let’s walk through an example based on Pictotest 2KAmp design which was presented at DesignCon 2025:
Current: 2,000A
Thickness: 5.6 mils
Temperature Rise: 10°C
Ambient Temperature: 55°C
Trace Length: 2500 mils**
** Trace Length parameter:
In general, in our calculation, we would like to take the worst-case, the longest trace from the VRM to the edge of the last ball to supply, but this not always is the right way to do so, we need to look at it from a different perspective and taking the realistic value.
For high-power power rails, it has become more common for designs to surround the ASIC with VRMs on all four (4) edges to have an equal current distribution at the BGA load Balls.
After a study, I found an accurate method to determine the trace length in a design under the ASIC by finding the mid-point, which is derived from the intersection of two crossing lines. An example of this method is shown below in Figure 2.
Furthermore, when placing the VRM on either of the four (4) edges of the ASIC we should have the following considerations:
VRM on one side - Taking the trace length from the VRM output to the far BGA balls on the load.
VRM on two sides - Taking the trace length after drawing a line between them and determining the mid-point from the line crossing.
VRM on three and four sides - Taking the trace length after drawing a two crossing lines between them and determining the mid-point from the line crossing.
Using the above parameters, we would get the following results, which are shown in Figure 3:
Required Trace Width = 270 Inch
Resistance = 1.2 uΩ
Voltage Drop = 2.5 mV
Power Loss = 5 W
As we saw before, this is a physically unrealistic number.
Adding the below parameters to our calculation will help to predict the IR drop with ~10% error vs. the IR drop simulation:
Drill size: This will be based on the via parameter and can be taken from the layout at the pad-stack section.
Package pitch: The package pitch will help to calculate the current path through the BGA.
Power Rail BGA Balls Quantity: The total BGA Balls on the relevant power rail.
Returning to our example, in Picotest 2KAmp EVK, they used the below values:
Drill size: 8 mils
Package pitch: 1 mm
Power Rail BGA Balls Quantity: 512
Using the above parameters, we would get the following results, which as shown in Figure 4:
Required Trace Width = 7.8 Inch
Resistance = 42 uΩ
Voltage Drop = 85 mV
Power Loss = 170 W
PDN Simulation Results:
After the layout is done, PDN Simulation results show a DC IR drop of 37.5 uΩ, we would get the following results:
If you want to use the calculator discussed in this blog, it can be found at the link below.
IR Drop Calculator Link:
Wrapping Up:
As we’ve explored, accurately predicting the IR drop in high-power PCB designs is essential for meeting power integrity requirements, especially in complex applications like AI and datacenter ASICs. The ability to forecast the necessary trace width and its impact on power loss before diving into simulations allows for more informed decisions from the outset of the design process.
The tools and formulas provided in this blog give a clear, first-pass approach to estimating the IR drop based on realistic parameters. However, it’s important to remember that these predictions should be refined through detailed simulations to capture all variables that affect the final design. Using a predictive calculator early on can help guide your decisions on copper thickness, via placement, and power rail design, ultimately helping to avoid costly design iterations later in the process.
By integrating these tools into your design workflow, you can confidently address power integrity challenges and ensure that your PCB design is prepared to handle high-current demands without compromising performance.
References:
Power Delivery Network Master Class on 2000A: How to Design, Simulation, and Validation, DesignCon 2025.
Idan Ben Ezra | Linkedin
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