The constant development of new and emerging technologies, such as Artificial Intelligence (AI), electric vehicles, and 5G/6G communication systems, are driving higher board densities than ever before. This has led to the popularity of Voltage Regulator Modules (VRMs) as a way to help alleviate space in the PCB design. Depending on the power requirements of an application, power supplies can consume a significant amount of real estate on a PCB design to achieve a stable and low noise PDN design. In this post, our goal is to show you the value of doing simple impedance measurements to assess the stability and performance of a PDN design for your PCB.
Why Do We Measure Impedance?
Impedance measurements provide a quick and easy method for assessing how well a PDN or a VRM can deliver stable voltage to the components and ICs downstream in the circuit. As we've seen previously, noise follows impedance -- High-Q impedance peaks will almost certainly correspond to noise seen in the design, whether in the power rail voltage ripple, transient response, or EMC/EMI measurements. After measuring impedance and performing a Non-Invasive Stability Measurement (NISM) invented by Steve Sandler of Picotest, we can easily identify instability in the VRM and the PDN. As an example, we will be using a 2-port probe to analyze two Wurth Elektronik DC/DC Step Down Modules on four different vendor evaluation boards (EVMs): 178033801, 178013801, 178021801, and 178031801. The 178033801 and 178013801 EVMs contain an LGA12-EP DC/DC Step Down Module, while the 178021801 and 178031801 EVMs contain an LGA16-EP Step Down Module.
At first glance, these EVMs appear to be great options for a design because they are micro-modules (uModules) and have a very small PDN footprint; however, to achieve proper performance and stability, additional components may need to be considered as part of the total power supply (or VRM uModule) footprint. As we've found, this is often the case, and as a hardware design engineer, it's your job to confirm which components may need to be added, and we will show you how to do that!
Setup for Impedance Measurements
Description | Model |
Vector Network Analyzer | |
2-Port PDN Transmission Line Probe Kit | |
Differential Amplifier | |
3D Probe Positioner (Probe Holder) | |
Wurth Elektronik EVMs | 178033801, 178013801, 178021801, and 178031801 |
Why do we specifically use the 2-port probe in this measurement? The 2-port shunt-through impedance measurement is considered the gold-standard for measuring a VRM's output impedance in the milli-Ohm and micro-Ohm region. Combining this with the use of a Vector Network Analyzer, such as the Bode 500 (or even the Bode 100), and a ground loop isolator, such as the J2113A, results in a simple, easy, and most importantly, accurate impedance measurement of your EVM. If you want to learn more about why using the P2102A 2-port probe is important for PDN impedance measurements, then check out this blog post. Additionally, there are a number of alternate setups for measuring PDN impedance. For example, if you prefer to use the Keysight E5061B VNA with the J2102B common mode transformer ground isolator, this blog post walks you step-by-step through performing that calibration and measurement.
Initial Measurement and Results
The impedance measurements on the Wurth Eval Boards, right out of the box, are displayed in Figure 2. The high-Q, sharp peaks in their impedance plots strongly indicate that all four boards contain instability in the control loops for these DC/DC converters. This is not uncommon! Hence, the importance of measuring your VRMs before design integration, including when you've been provided an example or reference design.
While all the boards are unstable, we will specifically focus on the 178013801 board with a 1Ω load at 0.85V. The instability in the design can be confirmed by performing a Non-Invasive Stability Measurement. As a general rule of thumb, stability margins below 45° can be considered unstable. Per NASA's Engineering Best Practices, 45° phase margin is considered generally acceptable, though not ideal, while 60° is typically the benchmark for stability. NISM performed on this board results in a stability margin of 7.957°, as shown in Figure 3. This phase margin is significantly lower than our acceptance criteria of 45°.
This is not a vendor-specific issue! As seen in another Signal Edge Solution blog post, found here, we highlight a TI EVM's instability as well. Failing to catch and address instability can lead to power supply-induced jitter and long-term reliability issues, including overheating, degradation of power components, or even complete failure of sensitive downstream ICs due to power supply and/or PDN oscillations. These challenges can result in costly redesigns or damage to critical systems. We want to emphasize that you cannot always trust vendor EVMs to be perfect reference designs and that you should always measure, verify, and possibly fix the example design before dropping it onto your board.
Fixing the Instability
To fix the instability in this design, ultimately, our goal is to reduce this sharp impedance peak. First, if the VRM is PMBus-controlled, we would tune the internal registers to adjust the control loop settings. This will directly impact the VRM's performance and stability. After doing so, if the design is still unstable, step two is to reduce the impedance peak by adding additional capacitance to the design.
In the 178013801 board, we do not have access to the control loop because the LGA12-EP is not PMBus-controlled. Thus, our only option for stabilizing the VRM would be to add capacitance.
How do we know how much capacitance we need? The equations are quite simple.
Looking back at Figure 3, we see that our instability occurs at 20.268kHz. To identify the inductance at this peak (Lpeak) using EQ(1), where:
f = frequency at the impedance peak, in our case this is 20.268 kHz.
XLpeak = impedance at frequency f, in our case this is 280.785 mΩ.
Lpeak = inductance at frequency f. This is what we will be solving for.
Solving this equation results in a Lpeak value of 1.7uH of inductance at 20.268kHz.
Next, to determine how much capacitance we need, we will now arbitrarily set a target impedance (Ztarget) value of 20mΩ, as shown by the green line in Figure 4. This will likely result in a Q < 2 which will provide a stable PDN design.
Finally, solving for EQ(3), for Capacitance (C), derives EQ(2). Thus, this yields the minimum additional capacitance required to flatten the 1.7uH impedance peak at 20.268kHz, which is 4.25mF of additional capacitance.
Wow! 4.25mF is a significant amount of capacitance to add to a design after it's already been created and laid out. Furthermore, this emphasizes that the total VRM footprint needs to be paid attention to. Hopefully, you were able to catch this instability before design integration, and you haven't reached the layout phase yet. Adding 4.25mF of output capacitors would significantly improve the stability and performance of the LGA12-EP.
To see the effects of adding this capacitance, come back for part 2 of this blog, coming soon!
References:
GN&C Engineering Best Practices For Human-Rated Spacecraft Systems
Evaluation Boards MagI³C-VDLM | Power Modules (MagI³C Series) | Würth Elektronik Product Catalog
Omicron Bode 500 Vector Network Analyzer | Signal Edge Solutions
Picotest J2113A Semi-Floating Differential Amplifier | Ground Loop Breaker | Signal Edge Solutions
Picotest P2102A 2-Port Probe | VRM, Power Plane, & Decoupling Measurements | Signal Edge Solutions
2-port PDN Impedance Measurement of a Power Supply | TI TPSM8D6C24 | Signal Edge Solutions
NISM using the P2102A Probe and E5061B VNA | Signal Edge Solutions
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